An example of the conventional vertical deflection circuit is discussed below with reference to FIG. 1.
In FIG. 1, (10) is a video signal input terminal, (12) is a luminance chrominance signal processing circuit (Y/C processing circuit), (14) is a synchronous separator circuit, (16) is a vertical synchronizing signal separator circuit, and (18) is a vertical count-down circuit.
A horizontal AFC circuit (22) comprises a phase comparator (24), a low-pass filter (26), a voltage control oscillator (28) oscillating at the frequency two-fold of the horizontal frequency, and a 1/2 frequency divider (30).
In addition, the vertical count-down circuit has been described in U.S. Pat. No. 4,231,060 and European Patent No. 249,987 A2.
(32) is a vertical deflection circuit, (34) is a horizontal deflection circuit, (36) is a flyback transformer, (38) is a Braun tube (cathode ray tube), (40) is a horizontal deflection coil, (2) is a vertical deflection coil, and (44) is an anode electrode of the cathode ray tube (38).
At the vertical deflection circuit (32), (46) is a ramp generator, (48) is an amplifier circuit, and (50) is an electric power amplifier circuit.
(52) is a rectifier circuit for detecting voltage variation and for supplying supply voltage to the vertical deflection circuit. In other words, conventionally, it is known that anode voltage of the cathode ray tube (38) changes raster dimension at the cathode ray tube (refer to, for example, U.S. Pat. No. 4,298,829 and U.S. Pat. No. 4,752,722). Therefore, the rectifier circuit (52) detects the variation in anode voltage by rectifying the secondary winding (36a) of the flyback transformer (36). The output (+B) of the rectifier circuit (52) drives the vertical deflection circuit (32) and corrects the vertical deflection output so as not to change the raster dimension. The correction of vertical deflection output in FIG. changes a current value of the constant current circuit (54) at the ramp generator (46) to correct a slope angle of the sawtooth wave.
The video signal input from the video signal input terminal (10) includes a reproduction signal from a video cassette recorder (VCR). During the picture search reproduction and still reproduction of the VCR, the horizontal synchronization of the video signal input from the video signal input terminal (10) may be disturbed. Also simultaneously, the cycle period of vertical synchronization may expand or contract per one cycle period to thereby disturb the vertical synchronization.
In other words, during the reproduction of the VCR, the horizontal synchronizing signal disturbs, whereby the horizontal AFC circuit (22) is unstable. Hence, there is a problem that a pulse width of the vertical pulse output from the vertical countdown circuit (18) which counts the output to form the vertical pulse may vary. Also, during the VCR reproduction, the cycle period of vertical synchronizing signal expands or contracts, whereby there is a problem that the cycle period of the vertical pulse expands or contracts.
Therefore, the amplitude of the sawtooth wave signal from the ramp generator (46) varies, so that the picture of cathode ray 10 tube (38) may longitudinally deflect.
Hence, a vertical deflection circuit, which has a constant amplitude for a sawtooth signal also during the VCR reproduction, has been disclosed in the Japanese Utility Laid-Open Gazette No. SHO 63-12971.
FIG. 2 is a circuit diagram of the vertical deflection circuit (32a). FIG. 3 shows waveforms of the respective components. The vertical pulse (FIG. 3(a)) from the input terminal (56) becomes a signal in FIG. 3(b) through a differentiating circuit (58) and is applied to the set input S of RS-FF (RS type flip-flop circuit) (60) to set the RS-FF (60). Then, as shown in FIG. 3(c), its Q output is at a high level "H", thereby turning on the control transistor (62) (at time t1 in FIG. 3).
Upon turning on the control transistor (62), as shown in FIG. 3(d), a capacitor (64) charged by a constant current circuit (54) starts to discharge, the discharge current flows through a resistance (66) and the collector--the emitter transistor (62). When voltage (VA) at node A of the upper end of the capacitor (64) falls to be lower than voltage (VB) at node B (the time t2 in FIG. 3), a transistor (70) constituting a comparator (68) is off and a transistor (72) is on.
Therefore, transistors (74) and (76) are on to reset the RS-FF (60).
Then, the Q output of RS-FF (60) is inverted to be at a "L" level, whereby the control transistor (62) is on. Hence, the capacitor (64) is charged corresponding to the constant current circuit (54) and thereafter the same operation as the above will be repeated.
The vertical deflection circuit, which is constant in amplitude, stops discharge from the capacitor (64) when the level of the sawtooth wave signal is a predetermined value during the discharge of capacitor (64). In other words, the comparator (68) detects that the level of sawtooth wave signal becomes the predetermined value to thereby inhibit the pulse input to the discharge control transistor (62).
As the result, the sawtooth wave of constant amplitude is generated at node A, amplified by the amplifier circuits (48) and (50), and thereafter supplied as the deflecting current to the vertical deflection coil (42).
However, in the circuit in FIG. 2, the charge starting timing of capacitor (64) is decided by use of the differential comparator (68). Reference voltage (voltage VB at node B) of comparator (68) is obtained by resistive-dividing supply voltage (+B) of power source terminal (78) by resistances (80) and (82), but the supply voltage is obtained by smoothening the horizontal flyback pulse, whereby a ripple noise for a horizontal cycle period, even a little, remains in the dc component. Therefore, voltage at node B will vary for the horizontal cycle period.
The ripple noise of the reference voltage (voltage at node B) causes the comparator (68) to malfunction and the RS-FF (60) may be inverted to turn off the control transistor (62). Thus, in the circuit in FIG. 2, the ripple noise changes before and after the charge starting timing, thereby creating a problem in that the amplitude of the sawtooth wave signal varies.
As the result, the amplitude of the sawtooth wave is not continuous so that the vertical interlace characteristic on the television picture plane will be deteriorated. If the vertical pulse is not fluctuated in pulse width but the cycle period of the vertical pulse only expands or contracts, it is considered that a clamping circuit is housed in the ramp generator.
The ramp generator housing therein the clamping circuit is shown in FIG. 4. In addition, in the FIG. 4 example, a control transistor (62a) is on to charge a capacitor (64a). Its waveform is shown in FIG. 5.
In FIG. 4, (84) a reference voltage generator circuit, which comprises a Zener diode of Zener voltage Vz, and (86) is an anti-reverse-current diode and its forward voltage is VD.
For the circuit in FIG. 4, the scanning start level of sawtooth wave signal, as shown in FIG. 5(b), is fixed to clamping voltage (VZ-VD) so as to stabilize the scanning.
In the circuit in FIG. 4, however, when the vertical pulse varies in width (W in FIG. 5), the discharge start timing also varies, thereby creating the problem that the amplitude of the sawtooth wave signal varies.
Moreover, as described in FIG. 1, supply voltage (+B) of vertical deflection circuit is generated by rectifying the horizontal flyback signal directly or indirectly by the rectifier circuit ((52) in FIG. 1). Therefore rising of the voltage, when the power source is on, is late. Hence, as shown in FIG. 6, when the sawtooth wave signal on rising exceeds the clamping voltage (VZ-VD), the sawtooth signal is clamped and the amplitude (L in FIG. 6) of the sawtooth wave signal does not vary continuously (T in FIG. 6).